{"product_id":"turbo-coding-hardware-acceleration-of-an-egprs-2-turbo-decoder-on-an-fpga-3838330986","title":"Turbo Coding: Hardware Acceleration of an EGPRS-2 Turbo Decoder on an FPGA","description":"\u003cp\u003e\u003cstrong\u003eISBN:\u003c\/strong\u003e 3838330986\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eAuthor:\u003c\/strong\u003e Kjeldsen, Jesper\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eCondition:\u003c\/strong\u003e New\u003c\/p\u003e\u003cp\u003eThis report presents a hardware implementation of an EGPRS-2 turbo decoder based on the soft-output Viterbi algorithm (SOVA). Here techniques for optimizing the implementation has been used to establish a Finite State Machine with Datapath (FSMD) design. EGPRS-2 is the second evolution of GPRS, a standard for wireless transmission of data over the most widespread mobile communication network in the world, GSM. The SOVA based decoder is implemented in Matlab and analyzed through profiling. Here a bottleneck is found which takes up 70 % of the decoders execution time, is found. This bottleneck is mapped to an FSMD implementation, where the datapath is determined through cost optimization techniques and a pipeline is also implemented. XILINX Virtex-5 is used as an implementation reference to estimate a decreased execution time of the hardware design. It shows that a factor 1277 improvement over the Matlab implementation can be achieved and that it is able to handle the maximum EGPRS-2 throughput speed of 2 Mbit\/s.\u003c\/p\u003e","brand":"Mia Karts","offers":[{"title":"Default Title","offer_id":51928798822688,"sku":"NEW3838330986","price":90.0,"currency_code":"USD","in_stock":false}],"url":"https:\/\/miakarts.com\/products\/turbo-coding-hardware-acceleration-of-an-egprs-2-turbo-decoder-on-an-fpga-3838330986","provider":"Miakarts Books","version":"1.0","type":"link"}