{"product_id":"writing-testbenches-functional-verification-of-hdl-models-1402074018-used","title":"Writing Testbenches: Functional Verification of HDL Models","description":"\u003cp\u003e\u003cstrong\u003eISBN:\u003c\/strong\u003e 1402074018\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eAuthor:\u003c\/strong\u003e Bergeron, Janick\u003c\/p\u003e\u003cp\u003e\u003cstrong\u003eCondition:\u003c\/strong\u003e Used\u003c\/p\u003e\u003cp\u003emental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven constrained-random transaction-level self-checking testbenches all made possible through the introduction of hardware verification languages (HVLs), such as e from Verisity and OpenVera from Synopsys. The state-of-art methodologies described in Writing Test benches will contribute greatly to the much-needed equivalent of a synthesis breakthrough in verification productivity. I not only highly recommend this book, but also I think it should be required reading by anyone involved in design and verification of today's ASIC, SoCs and systems. Harry Foster Chief Architect Verplex Systems, Inc. xviii Writing Testbenches: Functional Verification of HDL Models PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification.\u003c\/p\u003e","brand":"Mia Karts","offers":[{"title":"Default Title","offer_id":67820042879264,"sku":"USED1402074018","price":25.09,"currency_code":"USD","in_stock":true}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/0980\/7426\/3840\/files\/714t8YDuXOL.jpg?v=1792194285","url":"https:\/\/miakarts.com\/products\/writing-testbenches-functional-verification-of-hdl-models-1402074018-used","provider":"Miakarts Books","version":"1.0","type":"link"}